View LH79520_4111877.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LH79520
Preliminary data sheet
FEATURES
* Highly Integrated System-on-Chip * High Performance (77.4144 MHz CPU Speed) * ARM720TTM RISC Core - 32-bit ARM7TDMITM RISC Core - 8 kB Cache - MMU (Windows CETM Enabled) - Write Buffer * 32 kB On-Chip SRAM * Flexible, Programmable Memory Interface - SDRAM Interface - 15-bit External Address Bus - 32-bit External Data Bus - Two Segments (128 MB each) - SRAM/Flash/ROM Interface - 26-bit External Address Bus - 32-bit External Data Bus - Seven Segments (64 MB Each) * Multi-stream DMA Controller - Four 32-bit Burst-based Data Streams * Clock and Power Management - 32.768 kHz Oscillator for Real Time Clock - 14.7456 MHz Oscillator and On-chip PLL for CPU and Bus Clocks - Active, Standby, Sleep and Stop Power Modes - Externally-supplied Clock Options * Low Power Modes - Active Mode: 55 mA (MAX.) - Standby Mode: 35 mA (MAX.) - Sleep Mode: 5.5 mA (MAX.) - Stop Mode 2: 18 A * Watchdog Timer * Vectored Interrupt Controller - 16 Standard and 16 Vectored IRQ Interrupts - Hardware Interrupt Priority - Software Interrupts - FIQ Fast Interrupts * Three UARTs - 16-byte FIFOs for Rx and Tx - IrDA SIR Support - Supports Data Rates Up to 460.8 kb/s * Two 16-bit Pulse Width Modulators * Two Dual Channel Timer Modules * Real Time Clock - 32-bit Up-counter with Programmable Load - Programmable 32-bit Match Compare Register
System-on-Chip
* 64 Programmable General Purpose I/O Signals - Multiplexed with Peripheral I/O Signals * Programmable Color LCD Controller - Up to 800 x 600 Resolution - Supports STN, Color STN, AD-TFT, TFT - Supports 15 Shades of Gray - TFT: Supports 64 k Direct Colors or 256 Colors selected from a Palette of 64,000 Colors - Color STN: Supports 3,375 Direct Colors or 256 Colors Selected from a Palette of 3,375 Colors * Synchronous Serial Port - Supports Data Rates Up to 1.8452 Mb/s - Compatible with Common Interface Schemes - Motorola SPITM - National Semiconductor MICROWIRETM - Texas Instruments SSI * JTAG Debug Interface and Boundary Scan * 5 V Tolerant Digital I/O - XTALIN and XTAL32IN inputs are 1.8 V 10 %
DESCRIPTION
The LH79520, powered by an ARM720T, is a complete System-on-Chip with a high level of integration to satisfy a wide range of requirements and expectations. The LH79520 combines a 32-bit ARM720T RISC, Color LCD controller, Cache, Local SRAM, a number of essential peripherals such as Direct Memory Access, Serial and Parallel Interfaces, Infrared support, Timers, Real Time Clock, Watchdog Timer, Pulse Width Modulators, and an on-chip Phase Lock Loop. Debug is made simple by JTAG support. This high level of integration lowers overall system costs, reduces development cycle time and accelerates product introduction. The LH79520's fully static design, power management unit, low voltage operation (1.8 V Core, 3.3 V I/O), on-chip PLL, fast interrupt response time, on-chip cache and SRAM, powerful instruction set, and low power RISC core provide high performance. To build an advanced portable device, advanced processing capability is required. This capability must come with increased performance in the display system and peripherals, and yet demand less power from batteries. The LH79520 is an integrated solution to fit these needs.
Preliminary data sheet
1
LH79520
NXP Semiconductors
System-on-Chip
ORDERING INFORMATION
Table 1. Ordering information Package Type number Name LH79520N0Q000B1 LQFP176 Description plastic low profile quad flat package; 176 leads; body 20 x 20 x 1.4 mm SOT1017-1 Version
2
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
DEBUG/TEST INTERFACE
RESET
EXTERNAL INTERRUPTS
14.7456 MHz
32.768 kHz
OSCILLATOR, PLL POWER MANAGEMENT, and RESET CONTROL
REAL TIME CLOCK
TEST LOGIC / PIN MUXING
32KB SRAM
GENERAL PURPOSE I/O
ARM 720T
CONDITIONED EXTERNAL INTERRUPTS VECTORED INTERRUPT CONTROLLER I/O CONFIGURATION
SYNCHRONOUS SERIAL PORT
EXTERNAL BUS INTERFACE
STATIC MEMORY CONTROLLER
TIMER (4) INTERNAL INTERRUPTS
SDRAM CONTROLLER DMA CONTROLLER
WATCHDOG TIMER
DUAL CHANNEL PWM ADVANCED PERIPHERAL BUS BRIDGE
UART (3) IrDA INTERFACE
ADVANCED HIGH PERFORMANCE BUS (AHB)
COLOR LCD CONTROLLER
ADVANCED PERIPHERAL BUS (APB)
ADVANCED LCD INTERFACE
79520-1B
Figure 1. LH79520 block diagram
Preliminary data sheet
Rev. 01 -- 16 July 2007
3
LH79520
NXP Semiconductors
System-on-Chip
PIN CONFIGURATION
176 133 132
1
LH79520
44 45 88
89
002aad212
Figure 2. LH79520 pin configuration
4
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
SIGNAL DESCRIPTIONS
Table 2. LH79520 Signal Descriptions
PIN NO. 2-7 9-12 14-17 19-22 24-27 29-32 50-54 56-63 65-66 67-69 71-74 76-79 81-84 86-87 101 109 110 111 112 102 104 105 107 108 106 41 42 43 44 46 47 48 38 34 35 36 37 39 144 148 147 146 157 145 144 SIGNAL NAME TYPE DESCRIPTION MEMORY INTERFACE (MI) NOTES
A[25:0]
Output
Address Signals
D[31:0]
Input/Output
Data Input/Output Signals
1
SDCLK DQM3 DQM2 DQM1 DQM0 SDCKE nDCS1 nDCS0 nRAS nCAS nSDWE nCS6 nCS5 nCS4 nCS3 nCS2 nCS1 nCS0 nOE nBLE3 nBLE2 nBLE1 nBLE0 nWE nWAIT DEOT0 nDACK0 DREQ0 DEOT1 DACK1 DREQ1
Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Output Output Input Output Output Input
SDRAM Clock Data Mask Output to SDRAMs Data Mask Output to SDRAMs Data Mask Output to SDRAMs Data Mask Output to SDRAMs SDRAM Clock Enable SDRAM Chip Select SDRAM Chip Select Row Address Strobe Column Address Strobe SDRAM Write Enable Static Memory Controller Chip Select Static Memory Controller Chip Select Static Memory Controller Chip Select Static Memory Controller Chip Select Static Memory Controller Chip Select Static Memory Controller Chip Select Static Memory Controller Chip Select Static Memory Controller Output Enable Static Memory Controller Byte Lane Enable / Byte Write Enable Static Memory Controller Byte Lane Enable / Byte Write Enable Static Memory Controller Byte Lane Enable / Byte Write Enable Static Memory Controller Byte Lane Enable / Byte Write Enable Static Memory Controller Write Enable Static Memory Controller External Wait Control DMA CONTROLLER (DMAC) DMA 0 End of Transfer DMA 0 Acknowledge DMA 0 Request DMA 1 End of Transfer DMA 1 Acknowledge DMA 1 Request
1 1 1 1 1 1 1 1
1 1 1 1 1
1 1
1, 3 1 1 1 1 1 1, 3
Preliminary data sheet
Rev. 01 -- 16 July 2007
5
LH79520
NXP Semiconductors
System-on-Chip
Table 2. LH79520 Signal Descriptions (Cont'd)
PIN NO. 130 132 139 140 141 142 114 115 116 117 118 119 121 122 123 124 126 127 137 129 131 133 134 135 135 129 142 137 119 164 165 166 167 169 150 151 157 163 162 163 162 SIGNAL NAME TYPE DESCRIPTION COLOR LCD CONTROLLER (CLCDC) NOTES
LCDVD[17:0]
Output
LCD Panel Data bus
1
LCDENAB LCDFP LCDLP LCDDCLK LCDDCLKIN LCDVDDEN LCDCLS LCDSPS LCDREV LCDSPL LCDPS SSPFRM SSPCLK SSPEN SSPTX SSPRX PWM0 PWMSYNC0 PWM1 UARTRX0 UARTTX0 UARTIRRX0 UARTIRTX0
Output Output Output Output Input Output Output Output Output Output Output Output Output Output Output Input Output Input Output Input Output Input Output
LCD Data Enable Frame Pulse (STN), Vertical Synchronization Pulse (TFT) Line Synchronization Pulse (STN), Horizontal Synchronization Pulse (TFT) LCD Panel Data Clock LCD External Clock Input LCD Digital Supply Enable LCD Clock Signal for Gate Driver (AD-TFT, HR-TFT only) LCD Reset Signal for Row Display (AD-TFT, HR-TFT only) LCD Reverse Signal (AD-TFT, HR-TFT only) LCD Line Start Pulse (Left) (AD-TFT, HR-TFT only) LCD Power Save (AD-TFT, HR-TFT only) SYNCHRONOUS SERIAL PORT (SSP) SSP Serial Frame Output SSP Clock SSP Data Enable SSP Data Out SSP Data In PULSE WIDTH MODULATOR (PWM) PWM0 Output PWM0 Synchronizing Input PWM1 Output UART0 (U0) UART0 Received Serial Data Input UART0 Transmitted Serial Data Output UART0 InfraRed Receive UART0 InfraRed Transmit
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
6
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
Table 2. LH79520 Signal Descriptions (Cont'd)
PIN NO. 160 159 169 167 153 155 156 159 160 164 165 166 139 140 141 142 146 147 148 152 129 130 131 132 133 134 135 137 116 117 118 119 121 122 123 124 102 104 105 106 109 110 111 112 61 62 63 65 66 67 99 101 SIGNAL NAME UARTRX1 UARTTX1 UARTRX2 UARTTX2 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 TYPE UART1 (U1) Input Output Input Output UART1 Received Serial Data Input UART1 Transmitted Serial Data Output UART2 (U2) UART2 Received Serial Data Input UART2 Transmitted Serial Data Output 1 1 1 1 DESCRIPTION NOTES
GENERAL PURPOSE INPUT/OUTPUT (GPIO)
Input/Output
General Purpose I/O Signals - Port A
1
Input/Output
General Purpose I/O Signals - Port B
1
Input/Output
General Purpose I/O Signals - Port C
1
Input/Output
General Purpose I/O Signals - Port D
1
Input/Output
General Purpose I/O Signals - Port E
1
Input/Output
General Purpose I/O Signals - Port F. GPIO PF1 is only available when CLKINSEL is `0' (i.e. the external clock source is not being used).
1
Preliminary data sheet
Rev. 01 -- 16 July 2007
7
LH79520
NXP Semiconductors
System-on-Chip
Table 2. LH79520 Signal Descriptions (Cont'd)
PIN NO. 52 53 54 56 57 58 59 60 34 35 41 42 43 44 50 51 145 96 97 114 115 144 150 151 152 153 155 93 94 89 90 88 98 99 156 98 174 170 173 172 171 175 176 1 SIGNAL NAME PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 CTOUT1B nRESETIN nRESETOUT INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 XTALIN XTALOUT XTAL32IN XTAL32OUT CLKINSEL CLKIN CLKEN CLKOUT UARTCLK nTRST TMS TCLK TDI TDO TEST1 TEST2 nTSTA TYPE DESCRIPTION NOTES
Input/Output
General Purpose I/O Signals - Port G
1
Input/Output
General Purpose I/O Signals - Port H
1
COUNTER/TIMER (C/T) Output Input Output Input Input Input Input Input Input Input Input Input Output Input Output Input Input Output Output Input Input Input Input Input Output Input Input Input Counter/Timer Output Reset Input Reset Output External Interrupt Input External Interrupt Input External Interrupt Input External Interrupt Input External Interrupt Input External Interrupt Input External Interrupt Input External Interrupt Input Crystal Input Crystal Output 32.768 kHz Crystal Oscillator Input 32.768 kHz Crystal Oscillator Output External Clock Select External Clock Input (if CLKINSEL = HIGH at reset) External Clock Enable (if CLKINSEL = LOW at reset, then this pin functions as PF1) Clock Out (selectable from the internal bus clock or 32.768) External UART Clock Input (with CLKSEL = LOW) TEST INTERFACE JTAG Test Reset Input JTAG Test Mode Select Input JTAG Test Clock Input JTAG Test Serial Data Input JTAG Test Data Serial Output Tie LOW for Normal Operation (has internal pull-down). JTAG Debug Enable: Tie LOW for Normal Operation; pull HIGH to enable JTAG Debugging (has internal pull-down). Tie HIGH for Normal Operation (has internal pull-up). 1 1 1 1 1 1 1, 3 1 1 1 1 1 1 RESET, CLOCK, AND POWER CONTROLLER (RCPC)
8
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
Table 2. LH79520 Signal Descriptions (Cont'd)
PIN NO. 40 75 95 113 136 154 45 120 138 158 8 18 28 49 64 85 100 125 143 161 13 23 33 55 70 80 103 128 149 168 91 92 SIGNAL NAME TYPE DESCRIPTION POWER AND GROUND (GND) NOTES
VDDC
Power
Core Power Supply
VSSC
Ground
Core GND
VDD
Power
Input/Output Power Supply
VSS
Ground
Input/Output GND
VDDA VSSA
Power Ground
Analog Power Supply for PLLs and XTAL Oscillators Analog GND for PLLs and XTAL Oscillators
NOTES: 1. These pin numbers have multiplexed functions. 2. Signals preceded by `n' are Active LOW. 3. Immediately after reset, pin 144 can be programmed to function as INT5, DREQ1 or both. Software should avoid enabling both of these functions simultaneously. Pin 144 can also be programmed to function as nWAIT, rendering the INT5/DREQ1 choice unavailable.
Preliminary data sheet
Rev. 01 -- 16 July 2007
9
LH79520
NXP Semiconductors
System-on-Chip
NUMERICAL PIN LIST
Table 3. LH79520 Numerical Pin List PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 FUNCTION AT FUNCTION 2 FUNCTION 3 RESET nTSTA A25 A24 A23 A22 A21 A20 VDD A19 A18 A17 A16 VSS A15 A14 A13 A12 VDD A11 A10 A9 A8 VSS A7 A6 A5 A4 VDD A3 A2 A1 A0 VSS PH7 PH6 nBLE1 nBLE0 nOE nBLE3 nBLE2 TYPE5 Input Output Output Output Output Output Output Power Output Output Output Output Ground Output Output Output Output Power Output Output Output Output Ground Output Output Output Output Power Output Output Output Output Ground I/O I/O Output Output Output OUTPUT DRIVE7 None 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA 8 mA NOTES 1
10
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
Table 3. LH79520 Numerical Pin List (Cont'd) PIN NO. 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 FUNCTION AT FUNCTION 2 FUNCTION 3 RESET nWE VDDC PH5 PH4 PH3 PH2 VSSC nCS2 nCS1 nCS0 VDD PH1 PH0 PG7 PG6 PG5 VSS PG4 PG3 PG2 PG1 PG0 PF7 PF6 PF5 VDD PF4 PF3 PF2 D15 D14 VSS D13 D12 D11 D10 VDDC D9 D8 D18 D17 D16 D26 D25 D24 D23 D22 D21 D20 D19 D31 D30 D29 D28 D27 nCS6 nCS5 nCS4 nCS3 TYPE5 Output Power I/O I/O I/O I/O Ground Output Output Output Power I/O I/O I/O I/O I/O Ground I/O I/O I/O I/O I/O I/O I/O I/O Power I/O I/O I/O I/O I/O Ground I/O I/O I/O I/O Power I/O I/O OUTPUT DRIVE7 8 mA None 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA NOTES
Preliminary data sheet
Rev. 01 -- 16 July 2007
11
LH79520
NXP Semiconductors
System-on-Chip
Table 3. LH79520 Numerical Pin List (Cont'd) PIN NO. 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 FUNCTION AT FUNCTION 2 FUNCTION 3 RESET D7 D6 VSS D5 D4 D3 D2 VDD D1 D0 CLKINSEL XTAL32IN XTAL32OUT VDDA VSSA XTALIN XTALOUT VDDC nRESETIN nRESETOUT CLKIN PF1 VDD PF0 PE7 VSS PE6 PE5 PE4 nRAS nCAS PE3 PE2 PE1 PE0 VDDC INT7 INT6 PD7 LCDVD11 LCDVD10 LCDVD9 DQM3 DQM2 DQM1 DQM0 nDCS1 nDCS0 nSDWE SDCLK SDCKE UARTCLK CLKEN TYPE5 I/O I/O Ground I/O I/O I/O I/O Power I/O I/O Input Input Output Power Ground Input Output Power Input Output Input I/O Power I/O I/O Ground I/O I/O I/O Output Output I/O I/O I/O I/O Power I/O I/O I/O None None 4 mA None 2 mA None 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 4 4 1, 4 None None None 8 3 OUTPUT DRIVE7 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA None None 2 8 3 NOTES
12
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
Table 3. LH79520 Numerical Pin List (Cont'd) PIN NO. 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 FUNCTION AT FUNCTION 2 FUNCTION 3 RESET PD6 PD5 PD4 VSSC PD3 PD2 PD1 PD0 VDD LCDVD1 LCDVD0 VSS PC7 PC6 PC5 PC4 PC3 PC2 PC1 VDDC PC0 VSSC PB7 PB6 PB5 PB4 VDD INT5/DREQ1 CTOUT1B PB3 PB2 PB1 VSS INT4 INT3 PB0 PA7 VDDC PA6 INT0 PWM0 PWMSYNC0 INT2 INT1 nWAIT DACK1 DREQ0 nDACK0 DEOT0 LCDVD15 LCDVD14 LCDVD13 LCDVD12 LCDREV LCDENAB LCDSPL LCDFP LCDVD17 LCDLP LCDVD16 LCDDCLK LCDDCLKIN LCDVDDEN LCDCLS LCDSPS LCDVD5 LCDVD4 LCDVD3 LCDVD2 LCDVD8 LCDVD7 LCDVD6 LCDPS TYPE5 I/O I/O I/O Ground I/O I/O I/O I/O Power Output Output Ground I/O I/O I/O I/O I/O I/O I/O Power I/O Ground I/O I/O I/O I/O Power Input Output I/O I/O I/O Ground I/O Input I/O I/O Power I/O OUTPUT DRIVE7 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA 8 mA 2 mA 8 mA None 8 mA None 8 mA 8 mA 8 mA 8 mA None None 4 mA 2 mA 4 mA 4 mA None 4 mA None 2 mA 2 mA None 2 mA 4 4 4 4 4 4 4, 6 NOTES
Preliminary data sheet
Rev. 01 -- 16 July 2007
13
LH79520
NXP Semiconductors
System-on-Chip
Table 3. LH79520 Numerical Pin List (Cont'd) PIN NO. 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 FUNCTION AT FUNCTION 2 FUNCTION 3 RESET PA5 PWM1 VSSC PA4 PA3 VDD UARTIRTX0 UARTIRRX0 PA2 PA1 PA0 SSPTX VSS SSPRX TMS TDO TDI TCLK nTRST TEST1 TEST2 UARTRX2 UARTTX0 UARTRX0 SSPFRM SSPCLK SSPEN UARTTX2 UARTTX1 UARTRX1 CLKOUT DEOT1 TYPE5 I/O Output Ground I/O I/O Power Output Input I/O I/O I/O Output Ground Input Input Output Input Input Input Input Input OUTPUT DRIVE7 8 mA 4 mA None 4 mA 2 mA None 4 mA None 4 mA 4 mA 4 mA 4 mA None None None 4 mA None None None None None 1, 4 2 2 1, 4 4 1, 4 4 4 NOTES
NOTES: 1. Input with internal pull-up. 2. Input with internal pull-down. 3. Output is for crystal oscillator only, no drive capability. 4. Input with Schmitt Trigger. 5. I/O = Input/Output. 6. Software should avoid enabling the INT5 and DREQ1 functions simultaneously. 7. Output Drive Values shown are MAX. See `DC Specifications'. 8. Crystal Oscillator Inputs should be driven to a maximum of 1.8 V 10 %.
14
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
Table 4. LCD Data Multiplexing
STN PIN NO. LCD DATA SIGNAL MONO 4-BIT SINGLE PANEL DUAL PANEL MONO 8-BIT SINGLE PANEL DUAL PANEL COLOR SINGLE PANEL DUAL PANEL ALL TFT: ALL TFT: 5:5:5+I 5:6:5 ALL TFT: PALETTE DATA OR 16-BIT DIRECT BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 15
130 132 139 140 141 142 114 115 116 117 118 119 121 122 123 124 126 127
LCDVD17 LCDVD16 LCDVD15 LCDVD14 LCDVD13 LCDVD12 LCDVD11 LCDVD10 LCDVD9 LCDVD8 LCDVD7 LCDVD6 LCDVD5 LCDVD4 LCDVD3 LCDVD2 LCDVD1 LCDVD0 MLSTN3 MLSTN2 MLSTN1 MLSTN0 MLSTN7 MLSTN6 MLSTN5 MLSTN4 MLSTN3 MLSTN2 MLSTN1 MLSTN0 CLSTN7 CLSTN6 CLSTN5 CLSTN4
BLUE4 BLUE3 BLUE2 BLUE1 BLUE0
BLUE3 BLUE2 BLUE1 BLUE0 GREEN5
CLSTN3 GREEN4 GREEN4 CLSTN2 GREEN3 GREEN3 CLSTN1 GREEN2 GREEN2 CLSTN0 GREEN1 GREEN1
MUSTN7 MUSTN7 CUSTN7 CUSTN7 GREEN0 GREEN0 MUSTN6 MUSTN6 CUSTN6 CUSTN6 MUSTN5 MUSTN5 CUSTN5 CUSTN5 MUSTN4 MUSTN4 CUSTN4 CUSTN4 MUSTN3 MUSTN3 MUSTN3 MUSTN3 CUSTN3 CUSTN3 MUSTN2 MUSTN2 MUSTN2 MUSTN2 CUSTN2 CUSTN2 MUSTN1 MUSTN1 MUSTN1 MUSTN1 CUSTN1 CUSTN1 RED4 RED3 RED2 RED1 RED0
6
RED4 RED3 RED2 RED1 RED0 BLUE4
MUSTN0 MUSTN0 MUSTN0 MUSTN0 CUSTN0 CUSTN0 Intensity
NOTES: 1. The Intensity bit is identically generated for all three colors. 2. MUSTN = Monochrome Upper data bit for STN panel. 3. MLSTN = Monochrome Lower data bit for STN panel. 4. CUSTN = Color Upper data bit for STN panel. 5. CLSTN = Color Lower data bit for STN panel. 6. Connect to the LSB of the Red, Green, and Blue inputs of a 6:6:6 panel. 7. Recommended hookups for TFT 5:5:5 + Intensity and 5:6:5 are shown. This wiring requires the BGR bit in the LCD Control Register to be 0.
Table 5. LCD Control and Timing Signals
PIN 119 129 131 133 134 135 137 142 LCDFP LCDLP LCDDCLK LCDDCLKIN LCDVDDEN LCDENAB STN AND TFT AD-TFT, HR-TFT LCDPS LCDSPS LCDLP LCDDCLK LCDDCLKIN LCDCLS LCDSPL LCDREV DESCRIPTION Power Save (AD-TFT, HR-TFT only) Frame Pulse (STN), Vertical Synchronization Pulse (TFT) /Row Display Reset Line Synchronization Pulse (STN), Horizontal Synchronization Pulse (TFT) Panel Data Clock External Clock Input Digital Supply Enable/Gate Driver Clock Data Enable/ Line Start Pulse (Left) Reverse Signal (AD-TFT, HR-TFT only)
Preliminary data sheet
Rev. 01 -- 16 July 2007
15
LH79520
NXP Semiconductors
System-on-Chip
TOUCH SCREEN CONTR. CODEC IMAGER SSP DMA STN/ TFT/AD-TFT PWM PIO UART
FLASH/ SRAM/ SDRAM
LH79520
UART
IR
MEMORY CARD INTERFACE
SH FLA D R CA
79520-6A
Figure 3. LH79520 Application Diagram Example
SYSTEM DESCRIPTIONS ARM720T Processor
The LH79520 microcontroller features the ARM720T cached core with an Advanced High-Performance Bus (AHB) interface. The ARM720T features: * 32-bit ARM7TDMITM RISC Core * 8 kB Cache * MMU (Windows CE enabled) The processor is a member of the ARM7T family of processors. For more information, see the ARM document, `ARM720T (Rev 3) Technical Reference Manual', available on NXP's's website at www.nxp.com. The LH79520 MMU provides a means to map Physical Memory (PA) addresses to virtual memory addresses. This allows physical memory, which is con-
strained by hardware to specific addresses, to be reorganized at addresses identified by the user. These user identified locations are called Virtual Addresses (VA). When the MMU is enabled, Code and Data must be built, loaded, and executed using Virtual Addresses which the MMU translates to Physical Addresses. In addition, the user may implement a memory protection scheme by using the features of the MMU. Address translation and memory protection services provided by the MMU are controlled by the user. The MMU is directly controlled through the System Control Coprocessor, Coprocessor 15 (CP15). The MMU is indirectly controlled by a Translation Table (TT) and Page Tables (PT) prepared by the user and established using a portion of physical memory dedicated by the user to storing the TT and PT's.
16
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
Memory Architecture
An integrated SDRAM Controller and Static Memory Controller provide a glueless interface to external SDRAM, Flash, SRAM, ROM, and burst ROM. Three remap options for the physical memory are selectable by software, as shown in Figures 4, 5, and 6. Memory is exclusively Little Endian. SDRAM CONTROLLER The SDRAM Controller provides the interface between the internal bus and external (off-chip) SDRAM memory devices (Figure 2). The SDRAM Controller provides the following features: * Two independently controlled chip selects. * Transfers data between the controller and SDRAM in quad-word bursts. * Supports both 32-bit and 16-bit SDRAM. * Supports 2K, 4K, and 8K row address memory parts, i.e. typical 256M, 128M, 64M, and 16M parts, with 8, 16, or 32 DQ bits per device. * Two reset domains allow SDRAM contents to be preserved over a soft reset. STATIC MEMORY CONTROLLER (SMC) The SMC provides the interface between the internal bus and external (off-chip) memory devices. The LH79520 boots from 16-bit memory. The SMC address space is divided into eight memory banks of 64 MB each. The SMC supports: * Static Memory-mapped Devices including RAM, ROM, Flash, and Burst ROM * Asynchronous Operations: - Page Mode Reads for non-clocked memory - Burst Mode Reads for burst mode ROM * 8-, 16-, and 32-bit wide external memory data paths * Independent configuration for up to eight memory banks, each up to 64 MB * Programmable Parameters: - WAIT States (up to 32) - Bus Turnaround Cycles (1 to 16) - Initial and Subsequent Burst Read WAIT State for Burst ROM Devices. The Static Memory Controller (SMC) also supports an nWAIT input that can be used by an external device to vary the wait time.
0xFFFFFFFF 0xFFFF0000 0xFFFC0000 ADVANCED HIGH-PERFORMANCE BUS PERIPHERALS ADVANCED PERIPHERAL BUS PERIPHERALS
0xFFFFFFFF 0xFFFF0000 0xFFFC0000 ADVANCED HIGH-PERFORMANCE BUS PERIPHERALS ADVANCED PERIPHERAL BUS PERIPHERALS
RESERVED 0x80000000 INTERNAL STATIC MEMORY 0x60000000 EXTERNAL STATIC MEMORY 0x40000000 SDRAM 0x20000000 EXTERNAL STATIC MEMORY 0x00000000
79520-5
Figure 4. Memory Remap `00' and `11'
0xFFFFFFFF 0xFFFF0000 0xFFFC0000 ADVANCED HIGH-PERFORMANCE BUS PERIPHERALS ADVANCED PERIPHERAL BUS PERIPHERALS
RESERVED 0x80000000 INTERNAL STATIC MEMORY 0x60000000 EXTERNAL STATIC MEMORY 0x40000000 SDRAM 0x20000000 INTERNAL STATIC MEMORY 0x00000000
79520-4
Figure 5. Memory Remap `10'
RESERVED 0x80000000 INTERNAL STATIC MEMORY 0x60000000 EXTERNAL STATIC MEMORY 0x40000000 SDRAM 0x20000000 SDRAM 0x00000000
79520-3
DMA Controller
The DMA Controller provides support for DMAcapable peripherals. The LCD controller uses its own DMA port, connecting directly to memory for retrieving display data.
Figure 6. Memory Remap `01'
Preliminary data sheet
Rev. 01 -- 16 July 2007
17
LH79520
NXP Semiconductors
System-on-Chip
* Simultaneous servicing of up to 4 data streams * Three transfer modes are supported: - Memory to Memory - Peripheral to Memory - Memory to Peripheral * Identical source and destination capabilities * Transfer Size Programmable (Byte, Half-word, Word) * Burst Size Programmable * Address Increment or Address Freeze * Transfer Error indication for each stream via an interrupt * 16-word FIFO array with pack and unpack logic Handles all combinations of byte, half-word or word transfers from input to output.
Advanced LCD Interface peripheral also provides a bypass mode that allows the LH79520 to interface to the built-in timing ASIC in standard TFT and STN panels.
Synchronous Serial Port (SSP)
The SSP is a master-only interface for synchronous serial communication with slave peripheral devices that support protocols for Motorola SPI, National Semiconductor MICROWIRE, or Texas Instruments Synchronous Serial Interface. * Master-only operation * Programmable clock rate * Separate transmit FIFO and receive FIFO buffers, 16 bits wide, 8 locations deep * DMA for transmit and receive * Programmable interface protocols: Motorola SPI, National Semiconductor MICROWIRE, or Texas Instruments Synchronous Serial Port * Programmable data frame size from 4 to 16 bits * Independent masking of transmit FIFO, receive FIFO and receive overrun interrupts * Available internal loopback test mode.
Color LCD Controller (CLCDC)
The CLCDC provides all the necessary control and drive signals to interface directly with a variety of color and monochrome LCD panels. * Supports single and dual scan color and monochrome Super Twisted Nematic (STN) displays with 4- or 8-bit interfaces * Supports Thin Film Transistor (TFT) color displays * Programmable resolution up to 800 x 600 - 800 x 600 (16-bit color can only be supported at 65 Hz refresh rates with 800 x 600 resolution). * 15 gray-level mono, 3,375 color STN, and 64 k color TFT support * 1, 2, or 4 bits-per-pixel (BPP) for monochrome STN * 1-, 2-, 4-, or 8-BPP palettized color displays for color STN and TFT * True-color non-palettized, for color STN and TFT * Programmable timing for different display panels * 256-entry, 16-bit palette fast-access RAM * Frame, line and pixel clock signals * AC bias signal for STN or data enable signal for TFT panels * Patented grayscale algorithm * Interrupt Generation Events * Dual 16-deep programmable 32-bit wide FIFOs for buffering incoming data. ADVANCED LCD INTERFACE The Advanced LCD Interface peripheral allows for direct connection to ultra-thin panels that do not include a timing ASIC. It converts TFT signals from the Color LCD controller to provide the proper signals, timing and levels for direct connection to a panel's Row and Column drivers for AD-TFT, HR-TFT, or any technology of panel that allows for a connection of this type. The
Universal Asynchronous Receiver Transmitter (UART)
The LH79520 incorporates three UARTs. * Programmable use of UART0 or IrDA SIR input/output * Separate 16-byte transmit and receive FIFOs to reduce CPU interrupts * Programmable FIFO disabling for 1-byte depth * Programmable baud rate generator * Independent masking of transmit FIFO, receive FIFO, receive timeout and modem status interrupts * False start bit detection * Line Break generation and detection * Fully-programmable serial interface characteristics: - 5-, 6-, 7-, or 8-bit data word length - Even-, odd- or no-parity bit generation and detection - 1 or 2 stop bit generation * IrDA SIR Encode/Decode block, providing: - Programmable use of IrDA SIR or UART0 input/output - Supports data rates up to 115.2 Kbps half-duplex - Programmable internal clock generator, allowing division of the Reference clock in increments of 1 to 512 for low-power mode bit durations.
18
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
VARIATIONS FROM THE 16C550 UART The UART varies from the industry-standard 16C550 UART device in six ways: * Receive FIFO trigger levels are fixed at 8 bytes * Receive errors are stored in the FIFO, and do not generate an interrupt. * The internal register map address space and each register's bit function differ. The following 16C550 UART features are not supported: * 1.5 stop bits (1 or 2 stop bits only are supported) * The forcing stick parity function * Independent receive clock.
- FIQ interrupt request - Non-vectored IRQ interrupt request (software to poll IRQ source) - Vectored IRQ interrupt request (up to 16 channels total) * The Watchdog timer can only generate FIQ interrupt requests * External interrupt inputs programmable - Edge triggered or level triggered - Rising edge/active HIGH or falling edge/active LOW The 28 interrupt channels are shown in Table 6. Table 6. Interrupt Channels
CHANNEL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27-29 30 31 INTERRUPT SOURCE External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 Spare Internal Interrupt 0 COMRX (used for debug) COMTX (used for debug) SSP RX time-out interrupt SSPRXTO CLCD Combined Interrupt SSP SSPTXINTR SSP SSPRXINTR SSP SSPRORINTR SSP SSPINTR Counter/Timer0 Counter/Timer1 Counter/Timer2 Counter/Timer3 UART ch0 Rx UART ch0 Tx UART ch0 UART ch1 UART ch2 DMA Combined Unused RTC_ALARM WDT
Pulse Width Modulator (PWM)
* Two independent output channels with separate input clocks * Up to 16-bit resolution * Programmable synchronous mode support - Allows external input to start PWM * Programmable pulse width (duty cycle), interval (frequency), and polarity - Static programming: PWM is stopped - Dynamic programming: PWM is running - Updates duty cycle, frequency, and polarity at the end of a PWM cycle - Wide programming range.
Vectored Interrupt Controller
The Vectored Interrupt Controller combines the interrupt request signals from 20 internal and eight external interrupt sources and applies them, after masking and prioritization, to the IRQ and FIQ interrupt inputs of the ARM7TDMI processor core. The Interrupt Controller incorporates a hardware interrupt vector logic with programmable priority for up to 16 interrupt sources. This logic reduces the interrupt response time for IRQ type interrupts compared to solutions using software polling to determine the highest priority interrupt source. This significantly improves the real-time capabilities of the LH79520 in embedded control applications. * 20 internal and eight external interrupt sources - Individually maskable - Status accessible for software polling * IRQ interrupt vector logic for up to 16 channels with programmable priorities * All of the interrupt channels, with the exception of the Watchdog Timer interrupt, can be programmed to generate:
Preliminary data sheet
Rev. 01 -- 16 July 2007
19
LH79520
NXP Semiconductors
System-on-Chip
Reset, Clock, and Power Controller (RCPC)
The RCPC generates the various clock signals for the operation of the LH79520 and provides for an orderly start-up after power-on and during a wake-up from one of the power saving operating modes. The RCPC allows the software to individually select the frequency of the various on-chip clock signals as required to operate the chip in the most power-efficient mode. It features: * 14.7456 MHz crystal oscillator and PLL for on-chip Clock generation * External Clock input if on-chip oscillator and PLL are not used * 32.768 kHz crystal oscillator generating 1 Hz clock for Real Time Clock * Individually controlled clocks for peripherals and CPU * Clock source for UARTs is selectable between 14.7456 MHz crystal oscillator and external clock source
* Programmable clock prescalers for UARTs and PWMs * Five global power control modes are available: - Active - Standby - Sleep - Stop1 - Stop2 * CPU and Bus clock frequency can be changed on the fly * Selectable clock output * Hardware reset (nRESETIN) and software reset. The 32.768 kHz crystal oscillator is not required for chip operation, so it may be left out of the design to save power. If this crystal is not used, XTALIN should be pulled to VDD or VSS so the input does not float.
Table 7. Clock and Enable States for Different Power Modes (Using On-chip Oscillator and PLL) FUNCTION 14.7456 MHz Oscillator PLL Peripheral Clock CPU Clock ACTIVE ON ON ON ON STANDBY ON ON ON OFF SLEEP ON ON OFF OFF STOP1 ON OFF OFF OFF STOP2 OFF OFF OFF OFF
20
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
Real Time Clock
The RTC can provide a basic alarm function or long time base counter. This is achieved by generating an interrupt signal after counting for a programmed number of cycles of RTC input. Counting in one-second intervals is achieved by the use of a 1 Hz clock input to the RTC. The features of the RTC are: * 32-bit up counter with programmable load * Programmable 32-bit match compare register * Software maskable interrupt when counter and compare registers are identical. RTC input clock sources: * PLL clock * 32.768 kHz clock * 1 Hz clock (default).
Timer
The LH79520 incorporates two Timer modules, each comprising two 16-bit independently programmable timers. This gives a total of four independent timers. * Each timer has two operating modes: - Free-running mode: After reaching 0x0000 the timer wraps around to 0xFFFF and generates an interrupt request. It continues to count down from 0xFFFF. - Periodic timer mode: After reaching 0x0000 the timer is automatically reloaded with its programmed value and generates an interrupt request. It continues to count down from the loaded value. * Each timer contains a programmable pre-scaler: - Bus clock divided by 1, 16, or 256 * Timers can be cascaded to achieve longer timing periods * Carry-out of higher-order timer provides clock signal for next lower order timer * Possible timing ranges: - 215 (single timer) - 231 (two timers cascaded) - 247 (three timers cascaded) - 263 (four timers cascaded) * Output signal of lowest order timer is externally available as CTOUT1B signal.
Watchdog Timer
The Watchdog Timer provides hardware protection against malfunctions. It is a programmable timer to be reset by software at regular intervals. Failure to reset the timer will cause a FIQ interrupt. Failure to service the FIQ interrupt will then generate a System Reset. The features of the Watchdog Timer are: * Driven by the bus clock * 16 programmable time-out periods: 216 through 231 clock cycles * Generates a system reset (resets LH79520) or a FIQ Interrupt whenever a time-out period is reached * Software enable, lockout, and counter-reset mechanisms add security against inadvertent writes * Protection mechanism guards against interrupt-service failure: - The first WDT time-out triggers FIQ and asserts nWDFIQ status flag - If FIQ service routine fails to clear nWDFIQ, then the next WDT time-out triggers a soft reset.
Input/Output Configuration System
The registers provided by the IOCON System allow the user to directly control the pin multiplexing of the device; by setting or clearing bits in a set of registers, the user can configure the LH79520 for peripheral devices.
General Purpose Input/Output (GPIO)
The LH79520 provides up to 64 bits of programmable input/output. These eight 8-bit ports are Ports A through H, and are multiplexed with other signals. * Individually programmable input/output pins * All I/O ports default to Input on power-up.
Preliminary data sheet
Rev. 01 -- 16 July 2007
21
LH79520
NXP Semiconductors
System-on-Chip
ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings
PARAMETER DC Core Supply Voltage DC I/O Supply Voltage DC Analog Supply Voltage Storage Temperature SYMBOL VDDC VDD VDDA TSTG RATING -0.3 to 2.4 -0.3 to 4.6 -0.3 to 2.4 -55 to +125 UNIT V V V C
NOTE: These stress ratings are only for transient conditions. Operation at or beyond absolute maximum rating conditions may affect reliability and cause permanent damage to the device.
Recommended Operating Conditions
PARAMETER DC Core Supply Voltage (VDDC)1 DC I/O Supply Voltage (VDD) Clock Frequency
2 1
MINIMUM TYPICAL 1.62 V 3.0 V 1.62 V 10 MHz 0C -40C 25C 25C 1.8 V 3.3 V 1.8 V
MAXIMUM 1.98 V 3.6 V 1.98 V 77.4144 MHz +70C +85C
DC Analog Supply Voltage (VDDA) Commercial Operating Temperature Industrial Operating Temperature
NOTES: 1. Core Voltage should never exceed I/O Voltage after initial power up. See the section titled `Power Supply Sequencing'. 2. Using 14.7456 MHz Input Crystal and On-Chip PLL. Functional to DC when using external clock.
22
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
DC/AC SPECIFICATIONS (COMMERCIAL)
Unless otherwise noted, all data provided under commercial DC specifications are based on 0C to +70C, VDDC = 1.62 V to 1.98 V, VDD = 3.0 V to 3.6 V, VDDA = 1.62 V to 1.98 V.
DC Specifications (Commercial)
SYMBOL VIH VIL VIT+ VITVHYST PARAMETER CMOS input HIGH voltage CMOS input LOW voltage Positive Input threshold voltage (Schmitt trigger pins) Negative Input threshold voltage (Schmitt trigger pins) Schmitt trigger hysteresis CMOS output HIGH voltage VOH Output drive (2 mA type) Output drive (4 mA type) Output drive (8 mA type) CMOS output LOW voltage VOL Output drive (2 mA type) Output drive (4 mA type) Output drive (8 mA type) XTAL32IN XTALIN IIN IOZ IACTIVE ISLEEP ISTOP1 ISTOP2 ISTOP2 CIN COUT RPULL External Clock Input External Clock Input Input leakage current Output tri-state leakage current Active current Sleep current Stop1 current Stop2 current (RTC ON) Stop2 current (RTC OFF) Input Capacitance Output Capacitance Pull-up or Pull-down Resistance 1.62 1.62 -10 -10 43.5 27.5 3.9 500 34 18 4 4 33 1.8 1.8 2.6 2.6 2.6 2.6 0.4 0.4 0.4 0.4 1.98 1.98 10 10 55 35 5.5 1.60 1.20 0.40 MIN. TYP. MAX. UNIT 2.0 5.5 0.8 V V V V V V V V V V V V V V V A A mA mA mA A A A pF pF K VIN = VDD or GND VOUT = VDD or GND 3 3, 4 VIT+ - VITIOH = -50 A IOH = -2 mA IOH = -4 mA IOH = -8 mA IOL = 50 A IOL = 2 mA IOL = 4 mA IOL = 8 mA 2 2 1 1 1 CONDITIONS NOTES
ISTANDBY Standby current
NOTES: 1. Table 2 details each pin's buffer type. 2. P-P Sinusoidal; 0.0 V DC offset. 3. Running Typical Application over operating range. 4. Current measured with CPU stopped and all peripherals enabled.
AC Test Conditions
PARAMETER Supply Voltage (VDD) Core Voltage (VDDC) Input Pulse Levels Input Rise and Fall Times Input and Output Timing Ref. Levels RATING 3.0 to 3.6 1.62 to 1.98 VSS to VDD 2 VDD/2 UNIT V V V ns V
Preliminary data sheet
Rev. 01 -- 16 July 2007
23
LH79520
NXP Semiconductors
System-on-Chip
AC Specifications
All signals described in Table 8 relate to transitions after a reference clock signal. The illustration in Figure 7 represents all cases of these sets of measurement parameters; except for the Asynchronous Memory Interface -- which are referenced to Address Valid. The reference clock signals in this design are: * HCLK, the System Bus clock * PCLK, the Peripheral Bus clock (locked to HCLK in the LH79520) * SSPCLK, the Synchronous Serial Interface clock * UARTCLK, the UART Interface clock * LCDDCLK, the LCD Data clock from the LCD Controller * and SDCLK, the SDRAM clock. All signal transitions are measured from the 50 % point of the clock to the 50 % point of the signal. See Figure 7.
For outputs from the LH79520, tOVXXX (e.g. tOVA) represents the amount of time for the output to become valid from the rising edge of the reference clock signal. Maximum requirements for tOVXXX are shown in Table 8. The signal tOHXXX (e.g. tOHA) represents the amount of time the output will be held valid from the rising edge of the reference clock signal. Minimum requirements for tOHXXX are listed in Table 8. For Inputs, tISXXX (e.g. tISD) represents the amount of time the input signal must be valid before the rising edge of the clock signal. Minimum requirements for tISXXX are shown in Table 8. The signal tIHXXX (e.g. tIHD) represents the amount of time the memory output must be held valid from the rising edge of the reference clock signal. Minimum requirements are shown in Table 8.
REFERENCE CLOCK
tOVXXX tOHXXX
OUTPUT SIGNAL (O)
tISXXX tIHXXX
INPUT SIGNAL (I)
79520-34
Figure 7. LH79520 Signal Timing
24
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
Table 8. AC Signal Characteristics (Commercial)
SIGNAL TYPE LOAD DRIVE SYMBOL MIN. MAX. DESCRIPTION Data Output Valid, following Address Valid Data Output Invalid, following Address Valid 2 x tHCLK - 18 ns Input tIDD
2 x tHCLK - 18 ns + (nWAIT -1) x tHCLK
ASYNCHRONOUS MEMORY INTERFACE SIGNALS tOVD Output 50 pF D[31:0] 8 mA tOHD 3 x tHCLK - 6 ns tHCLK + 6 ns
Data Input Valid, following Address Valid Data Input Valid, following Address Valid (nWAIT states) Chip Select Output Valid, following Address Valid Chip Select Output Invalid, following Address Valid
tOVCS nCS6 - nCS0 Output 30 pF 8 mA tOHCS tOVBE nBLE[3:0] Output 30 pF 8 mA tOHBEW tOHBER tOVWE nWE Output 30 pF 8 mA tOHWE tOVOE nOE Output 30 pF 8 mA tOHOE nWAIT Input tISWAIT 3 x tHCLK - 6 ns 2 x tHCLK - 6 ns 2 x tHCLK - 6 ns 3 x tHCLK - 6 ns 3 x tHCLK - 6 ns
tHCLK + 6 ns
tHCLK + 10 ns
Byte Lane Enable Valid, following Address Valid Byte Lane Enable Invalid, following Address Valid; Write Cycle Byte Lane Enable Invalid, following Address Valid; Read Cycle
tHCLK + 10 ns 2 x tHCLK - 6 ns tHCLK + 10 ns
Write Enable Valid, following Address Valid Write Enable Invalid, following Address Valid Ouput Enable Valid, following Address Valid Ouput Enable Invalid, following Address Valid
2 x tHCLK - 18 ns
WAIT Input Valid, following Address Valid Address Valid Output Data Valid Output Data Hold Input Data Setup Input Data Hold
SYNCHRONOUS MEMORY INTERFACE SIGNALS A[25:0] Ouput 50 pF Output 50 pF D[31:0] Input nCAS nRAS nSDWE SDCKE DQM[3:0] nSDCS[1:0] SDCLK Output 50 pF Output 50 pF Output 30 pF Output 30 pF Output 30 pF Output 30 pF Output 30 pF 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA tOVA tOVD tOHD tISD tIDD tOVCA tOHCA tOVRA tOHRA tOVSDW tOHSDW tOVC0 tOHC0 tOVDQ tOHDQ tOVSC tOHSC tSDCLK 2 ns 19.37 ns 2 ns 10.5 ns 2 ns 10.5 ns 2 ns 10.5 ns 2 ns 10.5 ns 2 ns 10.5 ns 1.2 ns 5 ns 1.5 ns 10.5 ns 10.5 ns 11 ns
CAS Valid CAS Hold RAS Valid RAS Hold SDWE Write Enable Valid SDWE Write Enable Hold SDCKE Clock Enable Valid SDCKE Clock Enable Hold DQM Data Mask Valid DQM Data Mask Hold SDCS Data Mask Valid SDCS Data Mask Hold SDRAM Clock Period
Preliminary data sheet
Rev. 01 -- 16 July 2007
25
LH79520
NXP Semiconductors
System-on-Chip
Table 8. AC Signal Characteristics (Commercial) (Cont'd)
SIGNAL TYPE LOAD DRIVE SYMBOL MIN. MAX. DESCRIPTION tOVSSPFRM Output Valid, Referenced to SSPCLK tOVSSPEN Output Valid, Referenced to SSPCLK SSP Transmit Valid SSP Receive Setup Note 1
SYNCHRONOUS SERIAL PORT (SSP) SSPFRM SSPEN SSPTX SSPRX INTR[5:0] Output 50 pF Output 50 pF Output 50 pF Input Input 2 mA 2 mA 2 mA tOVSSPFRM tOVSSPENB tOVSSPOUT tISSSPIN 17 ns INTERRUPTS 14 ns 14ns 14ns
NOTES: 1. INTR[5:0] are asynchronous signals. Interrupts must be held Active until serviced in Level Sensitive Mode, and held Active for a minimum of 20 ns in Edge Sensitive Mode. 2. nDACK0, DACK1 and DREQ[1:0] are asynchronous signals. They must be held Active until serviced, for a minimum of 20 ns.
26
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
DC/AC SPECIFICATIONS (INDUSTRIAL)
Unless otherwise noted, all data provided under industrial DC specifications are based on -40C to +85C, VDDC = 1.62 V to 1.98 V, VDD = 3.0 V to 3.6 V, VDDA = 1.62 V to 1.98 V.
DC Specifications (Industrial)
SYMBOL VIH VIL VIT+ VITVHST PARAMETER CMOS input HIGH voltage CMOS input LOW voltage Positive Input thrueshold voltage (Schmitt trigger pins) Negative Input threshold voltage (Schmitt trigger pins) Schmitt trigger hysteresis CMOS output HIGH voltage VOH Output drive (2 mA type) Output drive (4 mA type) Output drive (8 mA type) CMOS output LOW voltage VOL Output drive (2 mA type) Output drive (4 mA type) Output drive (8 mA type) XTAL32IN XTALIN IIN IOZ IACTIVE ISLEEP ISTOP1 ISTOP2 ISTOP2 CIN COUT RPULL External Clock Input External Clock Input Input leakage current Output tri-state leakage current Active current Sleep current Stop1 current Stop2 current (RTC ON) Stop2 current (RTC OFF) Input Capacitance Output Capacitance Pull-up or Pull-down Resistance 1.62 1.62 -10 -10 43.5 27.5 3.9 500 34 18 4 4 33 1.8 1.8 2.6 2.6 2.6 2.6 0.4 0.4 0.4 0.4 1.98 1.98 10 10 1.60 1.20 0.40 MIN. TYP. MAX. UNIT 2.0 5.5 0.8 V V V V V V V V V V V V V V V A A mA mA mA A A A pF pF K VIN = VDD or GND VOUT = VDD or GND 3 3, 4 VIT+ - VITIOH = -50 A IOH = -2 mA IOH = -4 mA IOH = -8 mA IOL = 50 A IOL = 2 mA IOL = 4 mA IOL = 8 mA 2 2 1 1 1 CONDITIONS NOTES
ISTANDBY Standby current
NOTES: 1. Table 2 details each pin's buffer type. 2. P-P Sinusoidal; 0.0 V DC offset. 3. Running Typical Application over operating range. 4. Current measured with CPU stopped and all peripherals enabled.
AC Test Conditions
PARAMETER Supply Voltage (VDD) Core Voltage (VDDC) Input Pulse Levels Input Rise and Fall Times Input and Output Timing Ref. Levels RATING 3.0 to 3.6 1.62 to 1.98 VSS to VDD 2 VDD/2 UNIT V V V ns V
Preliminary data sheet
Rev. 01 -- 16 July 2007
27
LH79520
NXP Semiconductors
System-on-Chip
CURRENT CONSUMPTION BY OPERATING MODE Current consumption can depend on a number of parameters. To make this data more usable, the values presented in Table 9 were derived under the conditions presented here. Maximum Specified Value The values specified in the MAXIMUM column were determined using these operating characteristics: * All IP blocks either operating or enabled at maximum frequency and size configuration * Core operating at maximum power configuration * All I/O loads at maximum (50 pF) * All voltages at maximum specified values * Maximum specified ambient temperature. Typical The values in the TYPICAL column were determined using a `typical' application under `typical' environmental conditions and the following operating characteristics: * SPI, UART, PWMs, and Timer peripherals operating; all other peripherals disabled * LCD enabled with 320 x 240 x 16-bit color, 60 Hz refresh rate * I/O loads at nominal * Cache enabled * FCLK = 77.4 MHz; HCLK = 51.6 MHz * All voltages at typical values * Nominal case temperature. PERIPHERAL CURRENT CONSUMPTION In addition to the modal current consumption, Table 10 shows the typical current consumption for each of the on-board peripheral blocks. The values were determined with the peripheral clock running at maximum frequency, typical conditions, and no I/O loads.
Table 9. Current Consumption by Mode
SYMBOL PARAMETER ACTIVE MODE* ICORE IIO ICORE IIO ICORE IIO ILEAK ILEAK ILEAK Core Current I/O Current STANDBY MODE Core Current Current drawn by I/O SLEEP MODE Core Current Current drawn by I/O STOP1 MODE Leakage Current, Core and I/O STOP2 MODE (RTC ON) Leakage Current, Core and I/O STOP2 MODE (RTC OFF) Leakage Current, Core and I/O 18 A 35 A 2.96 mA 3.8 2 mA A 29.6 0.8 mA mA 33.6 9.6 mA mA TYP. UNITS
NOTE: *ICORE = 58 mA MAX., IIO = 19 mA MAX., all active
Table 10. Peripheral Current Consumption PERIPHERAL UARTs RTC DMA SSP Counter/Timers LCD TYPICAL 200 5 4.1 500 207 2.2 UNITS A A mA A A mA
28
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
AC Specifications (Industrial)
Table 11. AC Signal Characteristics (Industrial)
SIGNAL TYPE LOAD DRIVE SYMBOL MIN. MAX. DESCRIPTION
ASYNCHRONOUS MEMORY INTERFACE SIGNALS tOVD Output 50 pF D[31:0] 2 x tHCLK - 18 ns Input tIDD
2 x tHCLK - 18 ns + (nWAIT -1) x tHCLK
tHCLK + 6.5 ns 3 x tHCLK - 6 ns
8 mA tOHD
Data Output Valid, following Address Valid Data Output Invalid, following Address Valid Data Input Valid, following Address Valid (1 WAIT state) Data Input Valid, following Address Valid (nWAIT states) Chip Select Output Valid, following Address Valid Chip Select Output Invalid, following Address Valid
tOVCS nCS6 - nCS0 Output 30 pF 8 mA tOHCS tOVBE nBLE[3:0] Output 30 pF 8 mA tOHBEW tOHBER tOVWE nWE Output 30 pF 8 mA tOHWE tOVOE nOE Output 30 pF 8 mA tOHOE nWAIT Input tISWAIT 3 x tHCLK - 6 ns 2 x tHCLK - 6 ns 3 x tHCLK - 6 ns 3 x tHCLK - 6 ns
tHCLK + 6 ns
tHCLK + 10 ns
Byte Lane Enable Valid, following Address Valid Byte Lane Enable Invalid, following Address Valid; Write Cycle Byte Lane Enable Invalid, following Address Valid; Read Cycle
tHCLK + 10 ns 2 x tHCLK - 6 ns 2 x tHCLK - 6 ns tHCLK + 10 ns
Write Enable Valid, following Address Valid Write Enable Invalid, following Address Valid Ouput Enable Valid, following Address Valid Ouput Enable Invalid, following Address Valid
2 x tHCLK - 18 ns
WAIT Input Valid, following Address Valid Address Valid Output Data Valid Output Data Hold Input Data Setup Input Data Hold
SYNCHRONOUS MEMORY INTERFACE SIGNALS A[25:0] Ouput 50 pF Output 50 pF D[31:0] Input nCAS nRAS nSDWE SDCKE DQM[3:0] Output 50 pF Output 50 pF Output 30 pF Output 30 pF Output 30 pF 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA tOVA tOVD tOHD tISD tIDD tOVCA tOHCA tOVRA tOHRA tOVSDW tOHSDW tOVC0 tOHC0 tOVDQ tOHDQ 2 ns 2 ns 11 ns 2 ns 11 ns 2 ns 11 ns 2 ns 11 ns 1.2 ns 5 ns 1.5 ns 11 ns 10.5 ns 11.5 ns
CAS Valid CAS Hold RAS Valid RAS Hold SDWE Write Enable Valid SDWE Write Enable Hold SDCKE Clock Enable Valid SDCKE Clock Enable Hold DQM Data Mask Valid DQM Data Mask Hold
Preliminary data sheet
Rev. 01 -- 16 July 2007
29
LH79520
NXP Semiconductors
System-on-Chip
Table 11. AC Signal Characteristics (Cont'd)(Industrial)
SIGNAL nSDCS[1:0] SDCLK TYPE LOAD DRIVE Output 30 pF Output 30 pF 8 mA 8 mA SYMBOL tOVSC tOHSC tSDCLK 2 ns 19.37 ns MIN. MAX. 11 ns DESCRIPTION SDCS Data Mask Valid SDCS Data Mask Hold SDRAM Clock Period
SYNCHRONOUS SERIAL PORT (SSP) SSPFRM SSPEN SSPTX SSPRX INTR[5:0] Output 50 pF Output 50 pF Output 50 pF Input Input 2 mA 2 mA 2 mA tOVSSPFRM tOVSSPENB tOVSSPOUT tISSSPIN 17 ns INTERRUPTS Note 1 14 ns 14ns 14ns SSPFRM Output Valid, Referenced to SSPCLK SSPEN Output Valid, Referenced to SSPCLK SSP Transmit Valid SSP Receive Setup
NOTES: 1. INTR[5:0] are asynchronous signals. Interrupts must be held Active until serviced in Level Sensitive Mode, and held Active for a minimum of 20 ns in Edge Sensitive Mode. 2. nDACK0, DACK1 and DREQ[1:0] are asynchronous signals. They must be held Active until serviced, for a minimum of 20 ns.
EXTERNAL CLOCKS Table 12. External Clocks AC Specifications
SYMBOL tCLKIN tCLKINH tCLKINL tSSPCLK tSSPCLKH tSSPCLKL tUCLK tUCLKH tUCLKL DESCRIPTION CLKIN Period CLKIN HIGH Time CLKIN LOW TIme SSPCLK Period SSPCLK HIGH Time SSPCLK LOW Time UCLK UCLK HIGH Time UCLK LOW Time MIN. 6.66 2.8 2.8 1 0.4 0.4 1 0.4 0.4 UNIT ns ns ns PCLK PCLK PCLK PCLK PCLK PCLK
79520-58
tSSPCLK tSSPCLKH tSSPCLKL
Figure 9. Synchronous Serial I/F Clocks AC Timing
NOTES: 1. PCLK is the period chosen for the internal peripheral clock domain. 2. MAX. period is DC. See `Recommended Operating Conditions'.
tUCLKH tCLKIN tCLKINL tCLKINH
tUCLK tUCLKL
79520-59
Figure 10. External UARTs/SIR Clock AC Timing
79520-57
Figure 8. External Clock AC Timing
30
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
Static Memory Controller Waveforms
nWAIT INPUT The Static Memory Controller (SMC) supports an nWAIT input that can be used by an external device to extend the wait time during a memory access. The SMC samples nWAIT at the beginning of at the beginning of each system clock cycle. The system clock cycle in which the nCSx signal is asserted counts as the first wait state. See Figure 11. The SMC recognizes that nWAIT is active within 2 clock cycles after it has been asserted. To assure that the current access (read or write) will be extended by nWAIT, at least two wait states must be programmed for this bank of memory. If N wait states are programmed, then the Static Memory Controller (SMC) holds this state for N system clocks, or until the SMC detects that nWAIT is inactive, whichever occurs last. As the number of wait states programmed increases, the amount of delay before nWAIT must be asserted also increases. If only 2 wait states are programmed,
then nWAIT must be asserted in the clock cycle immediately following the clock cycle during which the nCSx signal is asserted. Once the SMC detects that the external device has deactivated nWAIT, the SMC will complete its access in 3 system clock cycles. The formula for the allowable delay between asserting nCSx and asserting nWAIT is:
tASSERT = (system clock period) x (Wait States - 1) (where Wait States is from 2 to 31.)
READ AND WRITE WAVEFORMS Figure 12 shows the waveform and timing for an External Static Memory Write. Figure 13 shows the waveform and timing for an External Static Memory Read, with one Wait State. Figure 14 shows the waveform and timing for an External Static Memory Read, with two Wait States. The signal tIDD is shown without a setup time, as measurements are made from the Address Valid point and HCLK is an internal signal, shown for reference only.
Preliminary data sheet
Rev. 01 -- 16 July 2007
31
LH79520
32
ADDRESS tIDD DATA tISWAIT DATA CAPTURED
79520-108
HCLK
(See Note 1)
A[23:0]
D[31:0]
nCSx
Figure 11. nWait Assertion
Rev. 01 -- 16 July 2007
nWE
NXP Semiconductors
nWAIT
nBLE[1:0]
(See Note 2)
nOE
System-on-Chip
Preliminary data sheet
NOTES: 1. HCLK is an internal signal, provided for reference only. 2. The corresponding byte lane enable(s) become active.
1 WAIT STATE
HCLK
System-on-Chip
(See Note 1)
Preliminary data sheet
ADDRESS tOHD tOVD DATA tOHCS tOVCS tOHWE tOVWE tOHBEW tOVBE
79520-30
A[23:0]
D[31:0]
nCSx
Figure 12. External Static Memory Write, One Wait State
Rev. 01 -- 16 July 2007
NXP Semiconductors
nWE
nWAIT
nBLE[1:0]
(See Note 2)
nOE
NOTES: 1. HCLK is an internal signal, provided for reference only. 2. The corresponding byte lane enable(s) become active. 3. 1 HCLK of nWE is the minimum amount of assertion time necessary before adding a Wait state.
LH79520
33
LH79520
34
1 WAIT STATE ADDRESS tIDD DATA tOHCS tOVCS tOHBER tOVBE tOHOE tOVOE DATA CAPTURED
79520-31
HCLK
(See Note 1)
A[23:0]
D[31:0]
nCSx
nWE
Figure 13. External Static Memory Read, One Wait State
Rev. 01 -- 16 July 2007
NXP Semiconductors
nWAIT
nBLE[1:0]
(See Note 2)
nOE
System-on-Chip
Preliminary data sheet
NOTES: 1. HCLK is an internal signal, provided for reference only. 2. The corresponding byte lane enable(s) become active.
2 WAIT STATES
System-on-Chip
HCLK (See Note 1) ADDRESS tOHD + 1 HCLK tOVD
Preliminary data sheet
DATA tOHCS + 1 HCLK tOVCS tOHWE + 1 HCLK tOVWE tOHBEW + 1 HCLK tOVBE
79520-32
A[23:0]
D[31:0]
Figure 14. External Static Memory Write, Two Wait States
Rev. 01 -- 16 July 2007
nCSx
NXP Semiconductors
nWE
nWAIT
nBLE[1:0] (See Note 2)
nOE
LH79520
NOTES: 1. HCLK is an internal signal, provided for reference only. 2. The corresponding byte lane enable(s) become active.
35
LH79520
NXP Semiconductors
System-on-Chip
tOVSSPFRM
tOVSSPTX
SSPCLK
SSPFRM
SSPTX
tISSPRX
Figure 15. Synchronous Serial Port Waveform
36
Rev. 01 -- 16 July 2007
SSPRX
Preliminary data sheet
79520-171
System-on-Chip
NXP Semiconductors
LH79520
SDRAM Memory Controller Waveforms
Figure 16 shows the waveform and timing for an SDRAM Burst Read (page already open). Figure 17 shows the waveform and timing for SDRAM to Activate a Bank and Write.
tSDCLK
SCLK
tOHXXX
SDRAMcmd
READ tOV tOVXXX
A[15:0] tOVA D[31:0] NOTES: DATA n + 2 DATA n 1. SDRAMcmd is the combination of nRAS, nCAS, nSDWE, and nSDCS(X). DATA n + 1 DATA n + 3 2. tOVXXX represents tOVRA, tOVCA, tOVSDW, or tOVSC. 3. tOHXXX represents tOHRA, tOHCA, tOHSDW, or tOHSC. 4. nDQM is LOW. 5. SDCKE is HIGH.
BANK, COLUMN
tISD tIHD
LH79520-35
Figure 16. SDRAM Burst Read
tSDCLK
SCLK tOVC0
SDCKE tOVXXX tOHXXX
SDRAMcmd
ACTIVE tOVA
WRITE
A[15:0] BANK, ROW tOVA D[31:0] tOVD NOTES: 1. SDRAMcmd is the combination of nRAS, nCAS, nSDWE, and nSDCS(X). 2. tOVXXX represents tOVRA, tOVCA, tOVSDW, or tOVSC. Refer to the AC timing table. 3. tOHXXX represents tOHRA, tOHCA, tOHSDW, or tOHSC. 4. nDQM is LOW. tOHD DATA BANK, COLUMN
79520-36
Figure 17. SDRAM Bank Activate and Write
Preliminary data sheet
Rev. 01 -- 16 July 2007
37
LH79520
NXP Semiconductors
System-on-Chip
External DMA Handshake Signal Timing
DREQ TIMING As Figure 18 shows, once asserted, DREQ0 or DREQ1 must not transition from LOW to HIGH again until after nDACK0 or DACK1 has been asserted. DACK/DEOT TIMING These timing diagrams indicate when nDACK0, DACK1, DEOT0 and DEOT1 occur in relation to an external bus access to/from the external peripheral that requested the DMA transfer.
Figure 19 shows the timing with relation to a single read or the last word of a burst read from the requesting peripheral. Figure 20 shows the timing with relation to a single write or the last word of a burst write to the requesting peripheral. The timing of DACK/DEOT may become unpredictable when a Write to SDRAM occurs just prior to a single word Write to the requesting peripheral. If the write buffer is enabled for the SDRAM Controller, this can cause the DACK/DEOT to occur an indeterminate number of cycles prior to the actual Write to the requesting peripheral.
DREQ MUST NOT CHANGE STATE
DREQ MAY TRANSITON tDREQ0L, tDREQ1L
DREQ0, DREQ1
DACK1
nDACK0
NOTE: tDREQ0L = DREQ0 LOW Pulse Width = 2 HCLK MIN. tDREQ1L = DREQ1 LOW Pulse Width = 2 HCLK MIN.
79520-158
Figure 18. DREQ Timing Restrictions
38
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
HCLK (See Note) A[23:0] ADDRESS
D[31:0]
DATA
nCSx
nWEN
nBLE[1:0]
nOE nDACK0/ DEOT0/DEOT1 DACK1
NOTE: * HCLK is an internal signal provided for reference only.
79520-156
Figure 19. Read, from Peripheral to Memory, Burst Size = 1
HCLK (See Note) A[23:0] ADDRESS
D[15:0]
DATA
nCSx
nWEN
nBLE[1:0]
nOE nDACK0/ DEOT0/DEOT1 DACK1
NOTE: * HCLK is an internal signal provided for reference only.
79520-157
Figure 20. Write, from Memory to Peripheral, Burst Size = 1
Preliminary data sheet
Rev. 01 -- 16 July 2007
39
LH79520
NXP Semiconductors
System-on-Chip
HCLK*
A[23:0]
ADDRESS
D[31:0]
DATA #1
DATA #2
DATA #3
DATA #4
nCSx
nWEN
nBLE[1:0]
nOE
nDACK0/DEOT0/DEOT1
DACK1
NOTE: * HCLK is an internal signal, provided for reference only.
79520-169
Figure 21. Read, Peripheral to Memory: Peripheral Burst Size = 4
40
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
Preliminary data sheet
ADDRESS ADDRESS + 2 ADDRESS ADDRESS + 2 ADDRESS ADDRESS + 2 ADDRESS ADDRESS + 2 LS DATA #1 nCSx MS DATA #1 LS DATA #2 MS DATA #2 LS DATA #3 MS DATA #3 LS DATA #4 MS DATA #4 nOE
79520-168
HCLK*
A[23:0]
D[31:0]
nWEN
Figure 22. Write, Memory to Peripheral: Burst Size = 4; Destination Width > External Access Width
Rev. 01 -- 16 July 2007
NXP Semiconductors
nBLE[1:0]
nDACK0/
DEOT0/ DEOT1
DACK1
LH79520
NOTE: * HCLK is an internal signal, provided for reference only.
41
LH79520
NXP Semiconductors
System-on-Chip
Color LCD Controller System Timing Waveforms
This section contains typical output waveform diagrams. STN HORIZONTAL TIMING Figure 23 presents typical horizontal timing waveforms for STN panels. Figure 23 shows that the CLCDC Clock (an input to the CLCDC) is scaled within the CLCDC and utilized to produce the LCDDCLK output. Figure 24 presents typical vertical timing waveforms for STN panels. TFT HORIZONTAL TIMING Figure 25 presents typical horizontal timing waveforms for TFT panels.
TFT VERTICAL TIMING Figure 26 presents typical vertical timing waveforms for TFT panels. AD-TFT AND HR-TFT HORIZONTAL TIMING WAVEFORMS Figure 27 presents typical horizontal timing waveforms for AD-TFT and HR-TFT panels. The ALI adjusts and delays the normal TFT timing for the Row and Column driver chips integrated into AD-TFT and HR-TFT panels. Other panels requiring the use of the ALI will have similar timing waveforms. AD-TFT AND HR-TFT VERTICAL TIMING
Figure 28 presents typical vertical timing waveforms for AD-TFT and HR-TFT panels. The power sequencing and register information is the same as for TFT vertical timing.
42
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
Preliminary data sheet
1 STN HORIZONTAL LINE TIMING0:HSW LCDDCLK IS SUPPRESSED DURING LCDLLP TIMING0:HBP TIMING0:PPL TIMING0:HFP HORIZONTAL BACK PORCH ENUMERATED IN 'LCDDCLKS' D001 D002 D.... DNNN HORIZONTAL FRONT PORCH ONE 'LINE' OF LCD DATA ENUMERATED IN 'LCDDCLKS'
79520-117
CLCDC CLOCK (INTERNAL) PeriphClkSel2:LCSRC PeriphClkCtrl2:LCDCLK LCDClkPrescale:LCDPSVAL
131 LCDLP (LINE SYNC PULSE) TIMING2:IHS
Figure 23. STN Horizontal Timing Diagram
Rev. 01 -- 16 July 2007
NXP Semiconductors
133 LCDDCLK (PANEL DATA CLOCK) TIMING2:PCD TIMING2:BCD TIMING2:IPC TIMING2:CPL LCDMux:PIN133
LCDVD[17:0] (LCD DATA) THE ACTIVE DATA LINES WILL VARY WITH THE TYPE OF STN PANEL: 4-BIT, 8-BIT, COLOR, OR MONO
LH79520
NOTE:
Circled numbers are LH79520 pin numbers.
43
LH79520
44
DISPLAY-DEPENDENT TURN-ON DELAY 1 STN FRAME DISPLAY-DEPENDENT TURN-OFF DELAY PANEL POSITIVE HIGH-VOLTAGE SUPPLY ACTIVE PANEL NEGATIVE HIGH-VOLTAGE SUPPLY ACTIVE PANEL LOGIC ACTIVE PANEL DATA CLOCK ACTIVE AC BIAS ACTIVE TIMING1:VSW = 0 TIMING1: VBP TIMING1:LPP TIMING1:VFP BACK PORCH ENUMERATED IN HORIZONTAL 'LINES' ALL 'LINES' FOR ONE FRAME FRONT PORCH ENUMERATED IN HORIZONTAL 'LINES' SEE 'STN HORIZONTAL TIMING DIAGRAM'
79520-116
VDD
VSS
135
LCDVDDEN (DISPLAY ENABLE)
133 LCDDCLK (PANEL DATA CLOCK) TIMING2:PCD TIMING2:BCD TIMING2:IPC TIMING2:CPL LCDMux:PIN133
Figure 24. STN Vertical Timing Diagram
Rev. 01 -- 16 July 2007
NXP Semiconductors
137 LCDENAB (AC BIAS) TIMING2:ACB
129 LCDFP (FRAME PULSE) TIMING1:IVS (See Note 2)
PIXEL DATA AND HORIZONTAL CONTROL SIGNALS FOR ONE FRAME
NOTES: 1. Signal polarties may vary for some displays. 2. LCDFP with TIMING1:VSW = 0 is only a single horizontal ine period.
System-on-Chip
Preliminary data sheet
3.
Circled numbers are LH79520 pin numbers.
System-on-Chip
Preliminary data sheet
1 TFT HORIZONTAL LINE TIMING0:HSW TIMING0:HBP TIMING0:PPL TIMING0:HFP HORIZONTAL BACK PORCH ENUMERATED IN 'LCDDCLKS' D001 D002 D.... DNNN HORIZONTAL FRONT PORCH ONE 'LINE' OF LCD DATA ENUMERATED IN 'LCDDCLKS'
79520-119
CLCDC CLOCK (INTERNAL) PeriphClkSel2:LCSRC PeriphClkCtrl2:LCDCLK LCDClkPrescale:LCDPSVAL
131 LCDLLP (HORIZ. SYNC PULSE) TIMING2:IHS
Figure 25. TFT Horizontal Timing Diagram
Rev. 01 -- 16 July 2007
NXP Semiconductors
133 LCDDCLK (PANEL DATA CLOCK) TIMING2:PCD TIMING2:BCD TIMING2:IPC TIMING2:CPL LCDMux:PIN133
LCDVD[17:0] (LCD DATA)
LH79520
NOTE:
Circled numbers are LH79520 pin numbers.
45
LH79520
46
DISPLAY-DEPENDENT TURN-ON DELAY 1 TFT FRAME DISPLAY DEPENDENT TURN-OFF DELAY PANEL POSITIVE HIGH-VOLTAGE SUPPLY ACTIVE PANEL NEGATIVE HIGH-VOLTAGE SUPPLY ACTIVE PANEL LOGIC ACTIVE PANEL DATA CLOCK ACTIVE DATA ENABLE TIMING1: VSW TIMING1:VBP TIMING1:LPP TIMING1: VFP BACK PORCH ENUMERATED IN HORIZONTAL 'LINES' ALL 'LINES' FOR ONE FRAME FRONT PORCH ENUMERATED IN HORIZONTAL 'LINES' SEE 'TFT HORIZONTAL TIMING DIAGRAM'
79520-118
VDD
VSS
See Note 2
135 LCDVDDEN (ENABLE FOR LOW-VOLTAGE DIGITAL LOGIC AND ANALOG SUPPLIES)
133 LCDDCLK (PANEL DATA CLOCK) TIMING2:PCD TIMING2:BCD TIMING2:IPC
Figure 26. TFT Vertical Timing Diagram
Rev. 01 -- 16 July 2007
NXP Semiconductors
137 LCDENAB (DATA ENABLE) TIMING2:IOE
129 LCDFP (VERTICAL SYNC PULSE) TIMING1:IVS
PIXEL DATA AND HORIZONTAL CONTROL SIGNALS FOR ONE FRAME
NOTES: 1. Signal polarties may vary for some displays. 2. The use of LCDVDDEN for high-voltage power control is optional on some TFT panels.
System-on-Chip
Preliminary data sheet
3.
Circled numbers are LH79520 pin numbers.
System-on-Chip
NXP Semiconductors
LH79520
1 AD-TFT or HR-TFT HORIZONTAL LINE
CLCDC CLOCK (INTERNAL) PERIPHCLKSEL2:LCSRC PERIPHCLKCTRL2:LCDCLK LCDCLKPRESCALE:LCDPSVAL (SHOWN FOR REFERENCE) LCDLP (HORIZONTAL SYNC PULSE)
TIMING0:HSW
INPUTS TO THE ALI FROM THE CLCDC
LCDDCLK (PANEL DATA CLOCK) TIMING2:PCD TIMING2:BCD TIMING2:IPC TIMING2:CPL LCDMux:PIN133 LCDVD[17:0] 16 x (TIMING0:PPL+1) TIMING0:HSW + TIMING0:HBP LCDENAB (INTERNAL DATA ENABLE)
001 002 003 004 005 006 007 008 PIXEL DATA
320
133 LCDDCLK
(DELAYED FOR HR-TFT)
LCDVD[17:0] (DELAYED FOR HR-TFT)
001 002 003 004 005 006
317 318 319 320
1 LCDDCLK ALITIMING2:SPLDEL
OUTPUTS FROM THE ALI TO THE PANEL
137 LCDSPL
(LINE START PULSE LEFT) 1 LCDDCLK
131 LCDLP
(HORIZONTAL SYNC PULSE)
ALITIMING1:LPDEL
ALITIMING1:PSCLS
ALITIMING2:PS2CLS2
135 LCDCLS
119 LCDPS
ALITIMING1:REVDEL
142 LCDREV
NOTE:
Circled numbers are LH79520 pin numbers.
79520-120
Figure 27. AD-TFT and HR-TFT Horizontal Timing Diagram
TIMING1:VSW LCDSPS (Vertical Sync) 1.5 s - 4 s LCDCLS (Gate Driver Clock) LCDVD[17:0] (LCD DATA) NOTE: LCDDCLK can range from 4.5 MHz to 6.8 MHz.
79520-20
Figure 28. AD-TFT and HR-TFT Vertical Timing Diagram
Preliminary data sheet
Rev. 01 -- 16 July 2007
47
LH79520
NXP Semiconductors
System-on-Chip
Reset, Clock, and Power Controller (RCPC) Waveforms
Figure 29 shows the method the LH79520 uses when coming out of Reset or Power On. Figure 30 shows external reset timing, and Table 13 gives the timing parameters. Table 13. Reset AC Timing
PARAMETER tOSC32 tOSC14 tRSTIW tRSTOV tRSTIH tRSTOH DESCRIPTION Oscillator stabilization time after Power Up (VDDC = VDDCMIN) Oscillator stabilization time after Power Up (VDDC = VDDCMIN) nRESETIN Pulse Width (once sampled LOW) nRESETIN LOW to nRESETOUT valid (once nRESETIN sampled LOW) nRESETIN hold extend to allow PLL to lock once XTAL is stable nRESETOUT hold relative to nRESETIN HIGH 1 2 3.5 10 MIN. TYP. MAX. 550 2.5 UNIT ms ms HCLK HCLK s HCLK
VDDCmin
VDDC tOSC32
XTAL32
XTAL14 tOSC14 tRSTIH
nRESETI tRSTOH
nRESETO
79520-37
Figure 29. PLL Start-up
tRSTIW
nRESETIN
tRSTOV tRSTOH
nRESETO
79520-60
Figure 30. External Reset
48
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
Power Supply Sequencing
The 1.8 V power supply must be energized before the 3.3 V supply. Otherwise, the 1.8 V supply may not lag the 3.3 V supply by more than 10 s. If a longer delay time is needed, the voltage difference between the two power supplies must be within 1.5 V during power supply ramp up. To prevent a potential latch-up condition, voltage should only be applied to input pins after the device is powered-up as described above.
NXP recommends that users implementing a system to meet industrial temperature standards should use an external oscillator rather than a crystal to drive the system clock input of the System-on-Chip. This change from crystal to oscillator will increase the robustness (i.e., noise immunity of the clock input to the SoC).
Assuring Proper Reset Behavior
A separate reset for the TAP controller and poweron was designed into the LH79520 to give the Designer control over how the chip boots up and to be useful for bringing up software and hardware using E-ICE. However, for the LH79520 to enter Normal mode, an initial reset pulse is required for the TAP controller when Power-on Reset is asserted. Figure 31 illustrates one method for assuring proper TAP controller reset. This is a recommendation; Designers should assess their requirements and implement a solution that satisfies them. This recommended circuit uses an external AND gate to AND the nRESETIN and nTRST signals, insuring that the TAP Controller gets reset with either signal, and the LH79520 always powers up in Normal Mode.
Low Operating Temperatures and Noise Immunity
The junction temperature, Tj, is the operating temperature of the transistors in the integrated circuit. The switching speed of the CMOS circuitry within the SoC depends partly on Tj, and the lower the operating temperature, the faster the CMOS circuits will switch. Increased switching noise generated by faster switching circuits could affect the overall system stability. The amount of switching noise is directly affected by the application executed on the SoC.
LH79520
nTRST nRESETIN
nTRST nRESETIN
79520-174
Figure 31. TAP Controller Reset Circuit Example
Preliminary data sheet
Rev. 01 -- 16 July 2007
49
LH79520
NXP Semiconductors
System-on-Chip
Printed Circuit Board Layout Practices
LH79520 POWER SUPPLY DECOUPLING The LH79520 has separate power and ground pins for different internal circuitry sections. The VDD and VSS pins supply power to I/O buffers, while VDDC and VSSC supply power to the core logic. Each of the VDD and VDDC pins must be provided with a low impedance path to the corresponding board power supply. Likewise, the VSS and VSSC pins must be provided with a low impedance path to the board ground. Each power supply must be decoupled to ground using at least one 0.1 F high frequency capacitor located as close as possible to a VDDx, VSSx pin pair on each of the four sides of the chip. If room on the circuit board allows, add one 0.01 F high frequency capacitor near each VDDx, VSSx pair on the chip. To be effective, the capacitor leads and associated circuit board traces connecting to the chip VDDx, VSSx pins must be kept to less than half an inch (12.7 mm) per capacitor lead. There must be one bulk 10 F capacitor for each power supply placed near one side of the chip. REQUIRED LH79520 PLL, VDDA, VSSA FILTER The VDDA pin supplies power to the chip PLL circuitry. VSSA is the ground return path for the PLL circuit. If the internal PLL circuit will be used, these pins must have a low-pass filter attached as shown in Figure 32.
Similarly, the VSSA path is from the IC pin to the high frequency capacitor, then to the low frequency capacitor, keeping the distance from the IC pin to the high frequency cap as short as possible.
CAUTION
Note that the VSSA pin specifically does not have a connection to the circuit board ground. The LH79520 PLL circuit has an internal DC ground connection to VSS (GND), so the external VSSA pin must NOT be connected to the circuit board ground, but only to the filter components.
UNUSED INPUT SIGNAL CONDITIONING Floating input signals can cause excessive power consumption. Unused inputs which do not include internal pull-up or pull-down resistors should be pulled up or down externally, to tie the signal to its inactive state. Some GPIO signals may default to inputs. If the pins which carry these signals are unused, software can program these signals as outputs, to eliminate the need for pull-ups or pull-downs. Power consumption may be higher than expected until such software executes. Some LH79520 inputs have internal pull-ups or pulldowns. If unused, these inputs do not require external conditioning. OTHER CIRCUIT BOARD LAYOUT PRACTICES All output pins on the LH79520 have fast rise and fall times. Printed circuit trace interconnection length must therefore be reduced to minimize overshoot, undershoot and reflections caused by transmission line effects of these fast output switching times. This recommendation particularly applies to the address and data buses. When considering capacitance, calculations must consider all device loads and capacitances due to the circuit board traces. Capacitance due to the traces will depend upon a number of factors, including the trace width, dielectric material the circuit board is made from and proximity to ground and power planes. Attention to power supply decoupling and printed circuit board layout becomes more critical in systems with higher capacitive loads. As these capacitive loads increase, transient currents in the power supply and ground return paths also increase. Add pull-up resistors to all unused inputs unless an internal pull-down resistor has been specified; see Table 3. (All pull-up/pull-down resistors must be 33 K MAX.) Consider all signals that are Inputs at Reset time.
VDDC (SOURCE)
VDDC LH79520 100 PIN 91 VDDA
+
22 F 0.1 F PIN 92 VSSA
79520-64
Figure 32. VDDA, VSSA Filter Circuit The Schottky diode shown in the schematic must have a low forward drop specification, to allow VDDA to quickly transition through the entire input voltage range. The power pin VDDA path must be a single wire from the IC package pin to the high frequency capacitor, then to the low frequency capacitor, and finally through the series resistor to the board power supply. The distance from the IC pin to the high frequency capacitor must be kept as short as possible.
50
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
SUGGESTED EXTERNAL COMPONENTS
Figure 33 shows the suggested external components for the 32.768 kHz crystal circuit to be used with the NXP LH79520. The NAND gate represents the logic inside the SoC. See the chart for crystal specifics.
Figure 34 shows the suggested external components for the 14.7456 MHz crystal circuit to be used with the NXP LH79520. The NAND gate represents the logic inside the SoC. See the chart for crystal specifics.
ENABLE INTERNAL TO THE LH79520 EXTERNAL TO THE LH79520 XTAL32IN XTAL32OUT
Y1
32.768 kHz R1 10 M C1 15 pF GND NOTES: 1. Y1 is a parallel-resonant type crystal. (See table) 2. The nominal values for C1 and C2 shown are for a crystal specified at 12.5 pF load capacitance (CL). 3. The values for C1 and C2 are dependent upon the cystal's specified load capacitance and PCB stray capacitance. 4. R1 must be in the circuit. 5. Ground connections should be short and return to the ground plane which is connected to the processor's core ground pins. 6. Tolerance for R1, C1, C2 is 5%. C2 18 pF GND
RECOMMENDED CRYSTAL SPECIFICATIONS PARAMETER 32.768 kHz Crystal Tolerance Aging Load Capacitance ESR (MAX.) Drive Level Recommended Part DESCRIPTION Parallel Mode 30 ppm 3 ppm 12.5 pF 50 k 1.0 W (MAX.) MTRON SX1555 or equivalent
79520-172
Figure 33. Suggested External Components, 32.768 kHz Oscillator (XTAL32IN and XTAL32OUT)
Preliminary data sheet
Rev. 01 -- 16 July 2007
51
LH79520
NXP Semiconductors
System-on-Chip
ENABLE INTERNAL TO THE LH79520 EXTERNAL TO THE LH79520 XTALIN XTALOUT
Y1
14.7456 MHz R1 1 M C1 18 pF GND C2 22 pF GND
RECOMMENDED CRYSTAL SPECIFICATIONS NOTES: 1. Y1 is a parallel-resonant type crystal. (See table) 2. The nominal values for C1 and C2 shown are for a crystal specified at 18 pF load capacitance (CL). 3. The values for C1 and C2 are dependent upon the cystal's specified load capacitance and PCB stray capacitance. 4. R1 must be in the circuit. 5. Ground connections should be short and return to the ground plane which is connected to the processor's core ground pins. 6. Tolerance for R1, C1, C2 is 5%. PARAMETER 14.7456 MHz Crystal Tolerance Stability Aging Load Capacitance ESR (MAX.) Drive Level Recommended Part DESCRIPTION (AT-Cut) Parallel Mode 50 ppm 100 ppm 5 ppm 18 pF 40 100 W (MAX.) MTRON SX2050 or equivalent
79520-173
Figure 34. Suggested External Components, 14.7456 MHz Oscillator
52
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
PACKAGE SPECIFICATIONS
LQFP176: plastic low profile quad flat package; 176 leads; body 20 x 20 x 1.4 mm SOT1017-1
c y X
132
89
A ZE
133
88
e E w bp pin 1 index
176 44 45
M
HE
A
A2
A1
(A3) Lp L detail X
1
w e bp D HD
M
v ZD B v
M
A
M
B
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.23 0.13 c 0.20 0.09 D(1) 20.2 19.8 E(1) 20.2 19.8 e 0.4 HD 22.2 21.8 HE 22.2 21.8 L 1 Lp 0.75 0.45 v 0.2 w 0.07 y 0.08 ZD(1) 1.5 1.3 ZE(1) 1.5 1.3
7 0
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT1017-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 07-07-07 07-07-07
Figure 35. Package outline SOT1017-1 (LQFP176)
Preliminary data sheet
Rev. 01 -- 16 July 2007
53
LH79520
NXP Semiconductors
System-on-Chip
21.25 0.4 1.70
17.2 NOTE: Dimensions in mm.
79520-155
Figure 36. Recommended PCB Footprint
54
Rev. 01 -- 16 July 2007
19.55
22.95
17.2
Preliminary data sheet
0.25
System-on-Chip
NXP Semiconductors
LH79520
REVISION HISTORY
Table 14. Revision history
Document ID LH79520_N_1 Modifications: * First NXP version based on the LH79520 data sheet of 20060330 Release date Data sheet status 20070716 Preliminary data sheet Change notice Supersedes LH79520 Data Sheet v1_3
Preliminary data sheet
Rev. 01 -- 16 July 2007
55
LH79520
NXP Semiconductors
System-on-Chip
1. Legal information
1.1 Data sheet status
Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
1.2
Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
1.3
Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
1.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
2. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
(c) NXP B.V. 2007. All rights reserved.
IMPORTANT NOTICE
Dear customer, As from June 1st, 2007 NXP Semiconductors has acquired the LH7xxx ARM Microcontrollers from Sharp Microelectronics. The following changes are applicable to the attached data sheet. In data sheets where the previous Sharp or Sharp Corporation references remain, please use the new links as shown below. For www.sharpsma.com use www.nxp.com/microcontrollers for indicated sales addresses use salesaddresses@nxp.com (email) The copyright notice at the bottom of each page (or elsewhere in the document, depending on the version) - Copyright (c) (year) by SHARP Corporation. is replaced with: - (c) NXP B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or phone (details via salesaddresses@nxp.com). Thank you for your cooperation and understanding, In addition to that the Annex A (attached hereto) is added to the document.
NXP Semiconductors
ANNEX A: Disclaimers (11)
1. t001dis100.fm: General (DS, AN, UM) General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. 2. t001dis101.fm: Right to make changes (DS, AN, UM) Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 3. t001dis102.fm: Suitability for use (DS, AN, UM) Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. 4. t001dis103.fm: Applications (DS, AN, UM) Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 5. t001dis104.fm: Limiting values (DS) Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. 6. t001dis105.fm: Terms and conditions of sale (DS) Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail.
7. t001dis106.fm: No offer to sell or license (DS) No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 8. t001dis107.fm: Hazardous voltage (DS, AN, UM; if applicable) Hazardous voltage -- Although basic supply voltages of the product may be much lower, circuit voltages up to 60 V may appear when operating this product, depending on settings and application. Customers incorporating or otherwise using these products in applications where such high voltages may appear during operation, assembly, test etc. of such application, do so at their own risk. Customers agree to fully indemnify NXP Semiconductors for any damages resulting from or in connection with such high voltages. Furthermore, customers are drawn to safety standards (IEC 950, EN 60 950, CENELEC, ISO, etc.) and other (legal) requirements applying to such high voltages. 9. t001dis108.2.fm: Bare die (DS; if applicable) Bare die (if applicable) -- Products indicated as Bare Die are subject to separate specifications and are not tested in accordance with standard testing procedures. Product warranties and guarantees as stated in this document are not applicable to Bare Die Products unless such warranties and guarantees are explicitly stated in a valid separate agreement entered into by NXP Semiconductors and customer. 10. t001dis109.fm: AEC unqualified products (DS, AN, UM; if applicable) AEC unqualified products -- This product has not been qualified to the appropriate Automotive Electronics Council (AEC) standard Q100 or Q101 and should not be used in automotive critical applications, including but not limited to applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customer's own risk. 11. t001dis110.fm: Suitability for use in automotive applications only (DS, AN, UM; if applicable) Suitability for use in automotive applications only -- This NXP Semiconductors product has been developed for use in automotive applications only. The product is not designed, authorized or warranted to be suitable for any other use, including medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk.

▲Up To Search▲

Price & Availability of LH79520

	To Download LH79520 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .